Senior SoC Digital Design Engineer - Low-Power AI Hardware

Meta; San Diego (CA); On-site; USD 146,000 - 209,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta is seeking a Digital Design Engineer to contribute to the development of advanced SoC and hardware solutions. You will work on ASIC digital architecture, RTL coding, and IP integration, collaborating with researchers and engineers to optimize low-power accelerators and state-of-the-art SoCs.

You will analyze performance/power, map algorithms to hardware, and drive micro-architecture along with verification and physical design teams.

Qualifications

• Bachelor’s degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
• 6+ years of experience as a hardware design engineer for production silicon shipped in volume.
• Experience in digital design µArchitecture, RTL coding, and micro-architecture development.
• Experience communicating technical design decisions and trade-offs to cross-functional partners such as verification, physical design, and architecture teams.

Responsibilities

• Contribute to ASIC digital µArchitecture and design.
• Assist in the performance/power analysis of the design and help meet power and performance targets.
• Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration.
• Collaborate with adjacent teams such as Verification, Physical Design, and Design for Test.
• Develop micro-architecture, RTL coding, and design verification for complex IPs.
• Drive the IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads.

Skills

Digital design architecture

RTL coding

Micro-architecture development

Cross-functional communication

Education

Bachelor’s degree in Computer Science or Computer Engineering

Job description

Meta is seeking a Digital Design Engineer to contribute to the development of advanced SoC and hardware solutions. You will work on ASIC digital architecture, RTL coding, and IP integration, collaborating with researchers and engineers to optimize low-power accelerators and state-of-the-art SoCs.

You will analyze performance/power, map algorithms to hardware, and drive micro-architecture along with verification and physical design teams.