Senior Digital Design Engineer: SoC & Interconnect RTL

Meta; San Diego (CA); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta seeks highly skilled Design Engineers to advance advanced technology solutions, including machine learning and network acceleration. You will design, implement, and optimize low-power accelerators, state-of-the-art SoCs, and custom silicon, collaborating with researchers and engineers across teams.

The role emphasizes digital design, micro-architecture development, RTL coding, and IP/sub-system integration to meet power and performance targets while driving innovative hardware for

Qualifications

• Experience in digital design μArchitecture and RTL coding.
• Ability to communicate design decisions to cross-functional teams.
• Hands-on hardware design experience for production silicon.

Responsibilities

• Contribute to ASIC digital μArchitecture and design.
• Analyze performance and power, helping meet targets.
• Map algorithms to hardware and specify IP/subsystem requirements.
• Collaborate with DV, Physical Design, and Verification teams.
• Develop micro-architecture, RTL, and verification for IPs.
• Lead interconnect micro-architecture with DV/PD partners.

Skills

Digital μArchitecture

RTL coding

Hardware design

Education

Bachelor's degree in CS/CE/related field

Job description

Meta seeks highly skilled Design Engineers to advance advanced technology solutions, including machine learning and network acceleration. You will design, implement, and optimize low-power accelerators, state-of-the-art SoCs, and custom silicon, collaborating with researchers and engineers across teams.

The role emphasizes digital design, micro-architecture development, RTL coding, and IP/sub-system integration to meet power and performance targets while driving innovative hardware for