Lead ASIC Design Engineer

OHO Group (Lithuania); San Jose (CA); Presencial; USD 200 000 - 320 000; Tempo integral

Resumo da oferta

OHO Group (Lithuania) invites a Lead ASIC Design Engineer to join a San Francisco Bay Area AI accelerator startup.

You will own RTL design and microarchitecture, collaborating with architecture, verification, software and system teams throughout the silicon development cycle. The role emphasizes high ownership from day one on complex SoCs, interconnects, and performance-critical fabrics.

Qualificações

• 10+ years of ASIC/SoC design experience with hands-on RTL development.
• Experience designing complex SoCs, NoCs, interconnects, fabrics or high-performance processors.
• Familiarity with PCIe, CXL or UCIe.
• Experience with GPUs, AI accelerators, CPUs, TPUs is highly desirable.
• Experience with HBM, memory controllers or coherent fabrics is a strong plus.

Responsabilidades

• Own RTL design and microarchitecture.
• Work on cache-coherent and non-coherent interconnects and associated protocols.
• Define and review microarchitectural specifications and translate them into robust, synthesizable RTL.
• Work closely with verification engineers on design validation, debugging and performance analysis.
• Collaborate with architecture, verification, software and system teams throughout the silicon development cycle.

Conhecimentos

RTL design

Microarchitecture

NoCs / interconnects

PCIe

CXL

UCIe

AI accelerators

GPUs

Memory controllers

HBM

Coherent fabrics

Formação académica

BS/MS/PhD in EE/CE/CS

Descrição da oferta de emprego

Lead ASIC Design Engineer – San Francisco Bay Area – AI Accelerator Startup

About the Role

A fast-moving startup in the Bay Area is looking for ASIC design engineers with strong experience across IP, architecture and microarchitecture within the AI accelerator space. Offering high ownership from day one and the opportunity to work with a world-class team of industry leaders from the top semiconductor companies, this is an exciting role for someone who wants to be a part of something from an early stage.

Key Responsibilities

• Own RTL design and microarchitecture.
• Work on cache-coherent and non-coherent interconnects and associated protocols.
• Define and review microarchitectural specifications and translate them into robust, synthesizable RTL.
• Work closely with verification engineers on design validation, debugging and performance analysis.
• Collaborate with architecture, verification, software and system teams throughout the silicon development cycle.

What We're Looking For

• 10+ years of ASIC/SoC design experience, with substantial hands-on RTL development.
• Experience designing complex SoCs, NoCs, interconnects, fabrics or high-performance processors.
• Familiarity with technologies such as PCIe, CXL or UCIe.
• Experience working on GPUs, AI accelerators, CPUs, TPUs is highly desirable.
• Experience with HBM, memory controllers or coherent fabrics is a strong plus.

Education

BS, MS or PhD in Electrical Engineering, Computer Engineering, Computer Science or a related field.