Senior ASIC Design Engineer - ML/Video/Network IPs, Equity

Meta; Helena (MT); On-site; USD 178,000 - 250,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration. The roles involve architecture exploration, micro-architecture development, and IP identification/integration, with collaboration across verification and emulation teams on test plans and debugging.

You will partner with the implementation team to close timing and power constraints, with a competitive compensation

Qualifications

• Bachelor's degree in CS/CE or related field
• 8+ years of micro-architecture and RTL development for complex IPs or SoC micro-architecture/design and integration
• RTL development using Verilog, SystemVerilog and HLS

Responsibilities

• Architecture exploration for ASIC designs.
• Micro-architecture development for complex IPs.
• Identify, select and integrate soft and hard IP; collaborate on test plans with verification and emulation teams.
• Coordinate with implementation to close timing and power.

Skills

Architecture exploration

Micro-architecture

IP identification

Collaboration with verification/emul

Timing/Power constraints

Education

Bachelor's degree in CS/CE or related field

8+ years in micro-architecture/RTL or SoC IP integration

Tools

Verilog

SystemVerilog

HLS

Job description

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration. The roles involve architecture exploration, micro-architecture development, and IP identification/integration, with collaboration across verification and emulation teams on test plans and debugging.

You will partner with the implementation team to close timing and power constraints, with a competitive compensation