ASIC Engineer, Design

Meta; Cheyenne (WY); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is seeking ASIC Design Engineers to build cutting-edge ASICs for ML, video transcoding and network acceleration. You will explore architectures, develop micro-architecture, and identify/integrate IP with verification and emulation teams to test plans and debugging.

Collaboration with implementation is essential to meet timing and power constraints. Preferred qualifications include CPU/NOC/memory subsystems experience and advanced degrees.

Qualifications

• Bachelor’s degree in CS/CE or related field (or equivalent).
• 8+ years in micro-architecture and RTL for complex IPs or SoC micro-architecture/Design & Integration.
• RTL development using Verilog, SystemVerilog and HLS.

Responsibilities

• Architecture exploration.
• Micro-architecture development.
• Soft and hard IP identification, selection and integration; collaborate with verification and emulation teams on test plans and debugging.
• Collaborate with implementation to meet timing and power targets.

Skills

RTL development

Verilog/SystemVerilog

HLS

Micro-architecture

SoC integration

Education

Bachelor's degree in CS/CE or related field

Master’s or PhD in EE/CS or related

Job description

Summary:

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

Required Skills:

ASIC Engineer, Design Responsibilities:

1. Architecture exploration
2. Micro-architecture development
3. Soft and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and debug
4. Collaboration with implementation team to close the design on timing and power

Minimum Qualifications:

Minimum Qualifications:

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
2. 8+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration
3. RTL development using Verilog, System Verilog and HLS

Preferred Qualifications:

Preferred Qualifications:

1. Experience in CPU, NOC, Memory and Peripheral Subsystems
2. Experience with Synthesis, Timing Closure and Formal Verification Methodology
3. Master’s or PhD degree in Electrical Engineering, Computer Science or related areas
4. Experience in data path development

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry:

Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affi­rmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].