Senior ASIC Design Engineer for ML & Networking

Meta; Salem (OR); Vor Ort; USD 178.000 - 250.000; Vollzeit

Zusammenfassung

Meta is seeking ASIC Design Engineers for its Infrastructure group to develop cutting-edge chips used in machine learning, video transcoding, and network acceleration. The role focuses on architecture exploration, micro-architecture development, and IP integration across verification and implementation teams.

The ideal candidate has extensive RTL experience in Verilog/SystemVerilog and related design methodologies, plus a strong background in timing and power optimization.

Qualifikationen

• Bachelor's degree in computer science, computer engineering, or equivalent practical experience.
• 8+ years of experience in micro-architecture and RTL development for complex control and data path IPs or experience in SoC micro-architecture, design and integration.
• RTL development using Verilog, SystemVerilog and HLS.

Aufgaben

• Architecture exploration.
• Micro-architecture development.
• IP identification, selection and integration with verification and emulation teams in test plan development and debug.
• Collaborate with implementation team to meet timing and power goals.

Kenntnisse

Architecture exploration

Micro-architecture development

RTL development (Verilog/SystemVerilog

IP identification & integration

Ausbildung

Bachelor's degree or equivalent

Tools

Synthesis tools

HLS

Jobbeschreibung

Meta is seeking ASIC Design Engineers for its Infrastructure group to develop cutting-edge chips used in machine learning, video transcoding, and network acceleration. The role focuses on architecture exploration, micro-architecture development, and IP integration across verification and implementation teams.

The ideal candidate has extensive RTL experience in Verilog/SystemVerilog and related design methodologies, plus a strong background in timing and power optimization.