Senior ASIC Architect for ML, Video & Network Accel

Meta; Cheyenne (WY); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is seeking ASIC Design Engineers to build cutting-edge ASICs for ML, video transcoding and network acceleration. You will explore architectures, develop micro-architecture, and identify/integrate IP with verification and emulation teams to test plans and debugging.

Collaboration with implementation is essential to meet timing and power constraints. Preferred qualifications include CPU/NOC/memory subsystems experience and advanced degrees.

Qualifications

• Bachelor’s degree in CS/CE or related field (or equivalent).
• 8+ years in micro-architecture and RTL for complex IPs or SoC micro-architecture/Design & Integration.
• RTL development using Verilog, SystemVerilog and HLS.

Responsibilities

• Architecture exploration.
• Micro-architecture development.
• Soft and hard IP identification, selection and integration; collaborate with verification and emulation teams on test plans and debugging.
• Collaborate with implementation to meet timing and power targets.

Skills

RTL development

Verilog/SystemVerilog

HLS

Micro-architecture

SoC integration

Education

Bachelor's degree in CS/CE or related field

Master’s or PhD in EE/CS or related

Job description

Meta is seeking ASIC Design Engineers to build cutting-edge ASICs for ML, video transcoding and network acceleration. You will explore architectures, develop micro-architecture, and identify/integrate IP with verification and emulation teams to test plans and debugging.

Collaboration with implementation is essential to meet timing and power constraints. Preferred qualifications include CPU/NOC/memory subsystems experience and advanced degrees.