Senior ASIC Design Engineer — ML/Video & Network Accel

Meta; Honolulu (HI); On-site; USD 178,000 - 250,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

The ideal candidate will perform architecture exploration, micro-architecture development, and IP integration, collaborating with verification, emulation and implementation teams to meet timing and power goals.

Qualifications

• Bachelor's degree in CS/CE or equivalent required.
• 8+ years of experience in micro-architecture and RTL development or SoC micro-architecture design and integration.
• RTL development using Verilog, SystemVerilog and HLS.

Responsibilities

• Architecture exploration for complex IP.
• Micro-architecture development for RTL design.
• Identify, select and integrate soft/hard IP with verification teams.
• Collaborate with implementation to close timing and power.

Skills

Architecture exploration

Micro-architecture development

IP identification & integration

Test plan development & debug

Education

Bachelor's degree in CS/CE or equivalent

8+ years in micro-architecture/RTL or SoC architecture

RTL development with Verilog, SystemVerilog & HLS

Job description

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

The ideal candidate will perform architecture exploration, micro-architecture development, and IP integration, collaborating with verification, emulation and implementation teams to meet timing and power goals.