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Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.
Minimum qualifications include a Bachelor's degree in a relevant field and 8+ years in micro-architecture/RTL development or SoC integration, with RTL using Verilog/SystemVerilog and HLS. Public compensation ranges from $178,000 to $250,000 per year, plus bonus, equity and benefits.
Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.
Minimum qualifications include a Bachelor's degree in a relevant field and 8+ years in micro-architecture/RTL development or SoC integration, with RTL using Verilog/SystemVerilog and HLS. Public compensation ranges from $178,000 to $250,000 per year, plus bonus, equity and benefits.