Senior ASIC Design Engineer for ML & Networking IPs

Meta; Juneau (AK); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

Responsibilities include architecture exploration, micro-architecture development and IP integration, with collaboration across verification and emulation teams to test plans and debug, and with the implementation team to close timing and power.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 8+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration.
• RTL development using Verilog, System Verilog and HLS.

Responsibilities

• Architecture exploration and micro-architecture development.
• Soft and hard IP identification, selection and integration with verification and emulation teams.
• Collaboration with implementation team to close design on timing and power.

Skills

Architecture exploration

Micro-architecture development

IP integration

Cross-team collaboration

Education

Bachelor's degree in CS/CE or equivalent

8+ years experience in micro-architecture/RTL

RTL development in Verilog/SystemVerilog

Tools

Verilog

SystemVerilog

HLS

Synthesis/Timing Closure

Job description

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

Responsibilities include architecture exploration, micro-architecture development and IP integration, with collaboration across verification and emulation teams to test plans and debug, and with the implementation team to close timing and power.