Senior ASIC Design Engineer — ML & Network Acceleration

Meta; Salt Lake City (UT); Vor Ort; USD 178.000 - 250.000; Vollzeit

Zusammenfassung

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

Responsibilities include architecture exploration, micro-architecture development, IP selection and integration with verification and emulation teams, and collaborating with the implementation team to meet timing and power targets.

Qualifikationen

• Bachelor's degree in Computer Science, Computer Engineering, or related field
• 8+ years of experience in micro-architecture and RTL development for complex IPs or SoC micro-architecture design
• RTL development using Verilog, SystemVerilog and HLS

Aufgaben

• Architecture exploration and micro-architecture development
• IP identification, selection and integration with verification and emulation teams
• Collaboration with implementation team to meet timing and power targets

Kenntnisse

RTL Verilog/SystemVerilog

SoC micro-architecture

IP integration

Ausbildung

Bachelor's degree in CS/CE or related field

Tools

Verilog

SystemVerilog

HLS

Jobbeschreibung

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

Responsibilities include architecture exploration, micro-architecture development, IP selection and integration with verification and emulation teams, and collaborating with the implementation team to meet timing and power targets.