Senior ASIC Architect for ML/Video & Network IP

Meta; City of Albany (NY); Presencial; USD 178.000 - 250.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Equity

Descripción de la vacante

Meta is hiring ASIC Design Engineers to build cutting edge ASICs for machine learning, video transcoding and network acceleration in the Infrastructure group. This role emphasizes architecture exploration, RTL development and IP integration across verification and implementation teams.

Minimum qualifications include a CS/CE degree and 8+ years in micro-architecture or SoC design, with RTL in Verilog/System Verilog. Preferred candidates have CPU/NOC/memory experience and advanced degrees.

Formación

• Experience in RTL development for complex control and data path IPs.
• Ability to identify and integrate IP blocks and collaborate across verification and emulation teams.
• Experience with timing closure, Synthesis and verification methodologies is a plus.

Responsabilidades

• Perform architecture exploration and micro-architecture development for ASICs.
• Identify, select and integrate soft and hard IP; coordinate with verification teams on test plans.
• Work with implementation teams to meet timing and power targets.
• Collaborate with verification and emulation teams in debugging and validation.
• Partner with CPU, NOC, memory and peripheral subsystems teams as needed.

Conocimientos

Architecture exploration

Micro-architecture development

Soft IP integration

Timing and power collaboration

Educación

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

8+ years in micro-architecture and RTL development or SoC micro-architecture/design

Herramientas

Verilog

SystemVerilog

HLS

Descripción del empleo

Meta is hiring ASIC Design Engineers to build cutting edge ASICs for machine learning, video transcoding and network acceleration in the Infrastructure group. This role emphasizes architecture exploration, RTL development and IP integration across verification and implementation teams.

Minimum qualifications include a CS/CE degree and 8+ years in micro-architecture or SoC design, with RTL in Verilog/System Verilog. Preferred candidates have CPU/NOC/memory experience and advanced degrees.