ASIC Engineer, Design (University Grad)

Meta; Austin (TX); On-site; USD 140,000 - 220,000; Full time

Job summary

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

Responsibilities include architecture exploration, micro-architecture development, IP identification and integration, and collaboration with verification and emulation teams in test plan development and debug, as well as with implementation to meet timing and power constraints.

Qualifications

• Bachelor's or PhD in a relevant field with strong hardware design experience.
• Strong micro-architecture and RTL experience for complex IPs/SoC integration.
• Familiarity with synthesis, timing closure and formal verification.

Responsibilities

• Architecture exploration for ASIC blocks within infrastructure.
• Micro-architecture development and RTL for control/data paths.
• Identify and integrate soft/hard IP; collaborate on verification and emulation.
• Work with implementation to close timing and power gates.

Skills

Micro-architecture design

RTL development

Verilog / SystemVerilog / HLS

CPU / NOC / Memory subsystems

Synthesis & Timing Closure

Education

Bachelor's degree in Computer Science, Computer Engineering or related field

PhD in CS/CE or related field (preferred)

Tools

Verilog

SystemVerilog

HLS

Job description

About

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

Responsibilities

• Architecture exploration
• Micro-architecture development
• Soft and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and debug
• Collaboration with implementation team to close the design on timing and power

Minimum Qualifications

• Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
• Currently has, or is in the process of obtaining a PhD degree in computer science, computer engineering, a relevant technical field, and/or equivalent practical experience
• Experience in micro-architecture and RTL development for complex control and data path IPs or experience in SoC micro-architecture, design and integration
• RTL development using Verilog, SystemVerilog and HLS Experience in data path development
• Experience in CPU, NOC, Memory and Peripheral Subsystems
• Experience with Synthesis, Timing Closure and Formal Verification Methodology