ASIC Engineer, Design

Meta; Phoenix (AZ); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is hiring ASIC Design Engineers in our Infrastructure organization to build cutting edge ASICs for machine learning, video transcoding and network acceleration.

Role involves architecture exploration, micro-architecture development and IP integration, with collaboration across verification, emulation, and implementation teams to close timing and power gaps. Positions require deep RTL experience (Verilog/SystemVerilog/HLS) and a strong SoC background.

Qualifications

• Bachelor's degree in CS/CE or equivalent.
• 8+ years in micro-architecture & RTL or SoC integration experience.
• RTL development using Verilog, SystemVerilog and HLS.

Responsibilities

• Architecture exploration and micro-architecture development for ASIC designs.
• Identify and integrate soft and hard IP; collaborate with verification/emulation teams on test plans and debugging.
• Collaborate with implementation to meet timing and power targets.

Skills

Architecture exploration

Micro-architecture development

IP identification & integration

Collaboration with verification & emu

Timing & power closure collaboration

Education

Bachelor's degree or equivalent in CS/CE/related field

8+ years micro-architecture & RTL or SoC integration

RTL development: Verilog, SystemVerilog, HLS

Job description

Summary:

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

Required Skills:

ASIC Engineer, Design Responsibilities:

1. Architecture exploration
2. Micro-architecture development
3. Soft and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and debug
4. Collaboration with implementation team to close the design on timing and power

Minimum Qualifications:

Minimum Qualifications:

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
2. 8+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration
3. RTL development using Verilog, System Verilog and HLS

Preferred Qualifications:

Preferred Qualifications:

1. Experience in CPU, NOC, Memory and Peripheral Subsystems
2. Experience with Synthesis, Timing Closure and Formal Verification Methodology
3. Master’s or PhD degree in Electrical Engineering, Computer Science or related areas
4. Experience in data path development

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry:

Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affi­rmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].