ASIC Engineer, Design

Meta; Olympia (WA); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is hiring ASIC Design Engineers in our Infrastructure organization to build cutting-edge ASICs for machine learning, video transcoding, and network acceleration.

The role focuses on architecture exploration, micro-architecture development, and IP selection and integration with verification teams to ensure proper test plans and debugging. Collaboration with the implementation team targets timing and power optimizations.

Qualifications

• Bachelor's degree or equivalent in a technical field is required.
• 8+ years in micro-architecture and RTL development for complex IPs or SoC micro-architecture experience.
• RTL development using Verilog, SystemVerilog and HLS.

Responsibilities

• Architecture exploration and micro-architecture development.
• Identification, selection and integration of soft and hard IP, coordinating with verification and emulation teams for test plans and debugging.
• Collaborate with implementation team to meet timing and power goals.

Skills

RTL development

Verilog

SystemVerilog

HLS

SoC micro-architecture

IP integration

Education

Bachelor's degree in CS/CE or equivalent

Tools

Verilog

SystemVerilog

HLS

Job description

Summary:

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

Required Skills:

ASIC Engineer, Design Responsibilities:

1. Architecture exploration

2. Micro-architecture development

3. Soft and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and debug

4. Collaboration with implementation team to close the design on timing and power

Minimum Qualifications:

Minimum Qualifications:

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

2. 8+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration

3. RTL development using Verilog, System Verilog and HLS

Preferred Qualifications:

Preferred Qualifications:

1. Experience in CPU, NOC, Memory and Peripheral Subsystems

2. Experience with Synthesis, Timing Closure and Formal Verification Methodology

3. Experience in data path development

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affi?

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].