Senior ASIC Design Engineer - ML Inference Acceleration

Amazon Web Services (AWS); Cupertino (CA); On-site; USD 183,000 - 248,000; Full time

Benefits offered by this job

Sign-on & RSUs

Health benefits

401(k) matching

Paid time off

Parental leave

Job summary

Annapurna Labs, an AWS subsidiary, is seeking an ASIC Design Engineer in Cupertino to design high-performance RTL for SOCs and integrate subsystems. You will work with cross‑functional teams across architecture, verification, and back‑end to meet power, area and timing targets.

The role requires a strong background in RTL design, SystemVerilog, and VLSI, plus hands-on scripting in Python. We value collaboration, mentoring, and a passion for hardware innovation.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• 5+ years RTL design for SOC.
• 5+ years in VLSI engineering.
• 5+ years with code quality tools including Spyglass, LINT, or CDC.

Responsibilities

• Implement and deliver high performance, area and power efficient RTL to meet design targets and specifications.
• Integrate subsystems into top level SOC with correct clock, reset, and DF T routing.
• Analyze design, microarchitecture or architecture to trade off features, power, performance or area.
• Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean designs with constraints.
• Perform lint and clock domain crossing quality checks on the design.
• Collaborate with architects, verification teams, and back-end teams to complete tasks.

Skills

Python scripting

Assertions

RTL debugging

Learn and Be Curious

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in EE/CE (preferred)

Tools

Spyglass

Lint

CDC

SystemVerilog

Job description

Annapurna Labs, an AWS subsidiary, is seeking an ASIC Design Engineer in Cupertino to design high-performance RTL for SOCs and integrate subsystems. You will work with cross‑functional teams across architecture, verification, and back‑end to meet power, area and timing targets.

The role requires a strong background in RTL design, SystemVerilog, and VLSI, plus hands-on scripting in Python. We value collaboration, mentoring, and a passion for hardware innovation.