Senior ASIC Design Engineer: Cloud ML Acceleration

Annapurna Labs; Cupertino (CA); On-site; USD 213,000 - 288,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. in Cupertino, CA is seeking an ASIC Design Engineer to design and optimize high‑performance RTL for SOCs and data‑center accelerators.

You will collaborate across architects, verification, and back‑end teams to meet aggressive power, area and timing targets. The role emphasizes SystemVerilog RTL development, lint/CDC checks and strong problem‑solving skills, with opportunities to work on full‑chip and subsystem integration and various design trade‑offs in a

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• 5+ years in RTL design for SOC.
• 5+ years in VLSI engineering.
• 5+ years with code quality tools including: Spyglass, LINT, or CDC.
• Experience in RTL coding and debug, performance/power/area trade-offs.
• Master's degree in electrical or computer engineering or equivalent.
• 5+ years of semiconductor design including full‑chip and subsystem integration.
• Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC constraints.
• Automation and scripting languages such as Python.
• Familiarity with data path design, interconnects, AXI protocol.
• Excellent analytical, problem solving, and communication skills.

Responsibilities

• As a key member of the ASIC design team, you will implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications.
• Integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/DFT signal routing
• Analyze design, microarchitecture or architecture to make trade-offs based on features, power, performance or area requirements.
• Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraints.
• Perform lint and clock domain crossing quality checks on the design.
• Work with architects, other designers, verification teams, pre- and post-silicon validation teams, synthesis, timing and back-end teams to accomplish your tasks.

Skills

Analytical skills

Problem solving

Communication skills

Python scripting

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical/Computer Engineering or equivalent

Tools

SystemVerilog RTL

Spyglass/LINT/CDC

SDC constraints

Assertions

Job description

Annapurna Labs (U.S.) Inc. in Cupertino, CA is seeking an ASIC Design Engineer to design and optimize high‑performance RTL for SOCs and data‑center accelerators.

You will collaborate across architects, verification, and back‑end teams to meet aggressive power, area and timing targets. The role emphasizes SystemVerilog RTL development, lint/CDC checks and strong problem‑solving skills, with opportunities to work on full‑chip and subsystem integration and various design trade‑offs in a