Senior ASIC Methodology Engineer - ML Acceleration

Amazon Inc.; San Diego (CA); Presencial; USD 213.000 - 288.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Health insurance

401(k) matching

Paid time off

Parental leave

Descripción de la vacante

Annapurna Labs, an Amazon unit, seeks an ASIC Physical Design Methodology Engineer to drive RTL-to-GDS flows for ML accelerator chips in advanced nodes.

You will collaborate with RTL, PD, and CAD teams, optimize CAD flows, and build scalable scripts (TCL/Python) while creating dashboards to track QoR and project progress. The role requires 7+ years of relevant experience and a Bachelor's in Electrical Engineering, based in Cupertino, CA.

Formación

• 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller).
• Bachelor's degree in Electrical Engineering or related field required. Master/PhD preferred.
• Experience with power islands and power gating; leading methodology and scripts.

Responsabilidades

• Define, develop and deploy STA/EMIR signoff and physical design methodologies (RTL2GDS) for ML accelerator chips.
• Drive CAD flow optimizations for Timing/EMIR signoff, PPA and throughput improvements.
• Work with EDA tool vendors to evaluate methods, resolve bugs and improve usability.
• Fine tune cloud infrastructure to improve compute and storage utilization for physical design work.
• Interface with RTL, PD, Package Design, DFT teams to improve methodologies and efficiencies.
• Troubleshoot digital tool flow usage and deploy scalable solutions; build dashboards for QoR/stats.

Conocimientos

ASIC design

Synthesis

STA

Physical design

Scripting (TCL/Python)

Power-aware design

Educación

Bachelor's degree in Electrical Engineering

Master's or Ph.D. in Electrical Engineering

Herramientas

EDA tools

Version control / CI/CD

Descripción del empleo

Annapurna Labs, an Amazon unit, seeks an ASIC Physical Design Methodology Engineer to drive RTL-to-GDS flows for ML accelerator chips in advanced nodes.

You will collaborate with RTL, PD, and CAD teams, optimize CAD flows, and build scalable scripts (TCL/Python) while creating dashboards to track QoR and project progress. The role requires 7+ years of relevant experience and a Bachelor's in Electrical Engineering, based in Cupertino, CA.