ASIC Design Engineer: Cloud-Scale ML Acceleration

Amazon Web Services (AWS); Cupertino (CA); Presencial; USD 157.000 - 213.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Health insurance

401(k) matching

Paid time off

Parental leave

Descripción de la vacante

Amazon Web Services (AWS) Annapurna Labs is seeking an ASIC Design Engineer to help trail-blaze new technologies for high-performance, power-efficient RTL designs in our Cupertino, CA data-center ecosystem.

You will develop SystemVerilog RTL, run synthesis and timing analyses, and collaborate with architects, verification teams, and back-end engineers to ensure quality releases across IP blocks and SoCs.

Formación

• Bachelor's degree in Electrical Engineering or related field.
• Experience debugging architecture, algorithms, functionality and performance.

Responsabilidades

• Develop high-performance, area- and power-efficient RTL designs to meet project specs.
• Analyze designs, microarchitectures, and architectures to optimize trade-offs between features, power, performance and area.
• Create microarchitectures, implement SystemVerilog RTL, deliver synthesis and timing-clean designs with constraints.
• Perform lint and clock domain crossing quality checks to ensure design integrity.
• Collaborate with architects, designers, verification specialists, pre- and post-silicon teams, and back-end experts.

Conocimientos

RTL design

SystemVerilog

Microarchitectures

Lint checks

Collaboration

Python

Perl

Educación

Bachelor's degree in Electrical Engineering

Master's degree

Herramientas

Synthesis tools

Formal verification tools

Descripción del empleo

Amazon Web Services (AWS) Annapurna Labs is seeking an ASIC Design Engineer to help trail-blaze new technologies for high-performance, power-efficient RTL designs in our Cupertino, CA data-center ecosystem.

You will develop SystemVerilog RTL, run synthesis and timing analyses, and collaborate with architects, verification teams, and back-end engineers to ensure quality releases across IP blocks and SoCs.