Senior ASIC Design Methodology Engineer

Amazon Inc.; Cupertino (CA); Vor Ort; USD 213.000 - 288.000; Vollzeit

Benefits dieser Stelle

Health insurance (medical, dental, VSP

401(k) matching

Paid time off

Parental leave

RSUs

Zusammenfassung

Annapurna Labs, part of Amazon, is seeking an ASIC Physical Design Methodology Engineer to develop advanced STA/EMIR signoff methods and optimize CAD flows for ML accelerator chips in 16nm or smaller nodes. The role collaborates across RTL, CAD, packaging and DFT teams and requires strong scripting skills.

Public cloud hardware teams rely on scalable design flows and robust QoR dashboards. Candidates should have a deep background in low-power design, tool flow troubleshooting, and experience

Qualifikationen

• 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience.
• Bachelor's degree in Electrical Engineering or a related field.
• Knowledge of implementing chips with multiple power islands and power gating.
• Experience leading or solely developing methodology and scripts for physical synthesis.
• Experience low power design techniques.
• Experience leading technical initiatives and key deliverables.
• Experience with version control systems and CI/CD pipeline implementation.

Aufgaben

• Define, develop and deploy innovative STA/EMIR signoff and physical design methodologies (RTL2GDS) for ML Accelerator chips in advanced nodes.
• Drive optimizations in CAD flows/methodologies for Timing/EMIR signoff, PPA and TAT improvements.
• Work with EDA tool vendors to evaluate new methods, resolve bugs, improve usability.
• Fine tune cloud infrastructure to improve compute and storage utilization for physical design work.
• Interface directly with RTL, Physical Design, Package Design, DFT teams to improve methodologies and efficiencies.
• Be able to independently troubleshoot digital tool flow usage and deploy solutions.
• Fluent in scripting languages such as TCL, Python, etc. and able to build scalable and efficient flows to support parallel design developments.
• Create Dashboard and Central reports for project tracking and visualizing QoR/stats.

Kenntnisse

ASIC implementation

RTL/physical design

Scripting (TCL, Python)

CAD/EDA flows

CI/CD pipelines

Ausbildung

Bachelor's degree in Electrical Engineering or related field

Master's or Ph.D. in Electrical Engineering (preferred)

Tools

CI/CD pipelines

Jobbeschreibung

Annapurna Labs, part of Amazon, is seeking an ASIC Physical Design Methodology Engineer to develop advanced STA/EMIR signoff methods and optimize CAD flows for ML accelerator chips in 16nm or smaller nodes. The role collaborates across RTL, CAD, packaging and DFT teams and requires strong scripting skills.

Public cloud hardware teams rely on scalable design flows and robust QoR dashboards. Candidates should have a deep background in low-power design, tool flow troubleshooting, and experience