ASIC Design Engineer II — Trailblazing High-Perf SoCs

Annapurna Labs; San Diego (CA); On-site; USD 154,000 - 215,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Flexible working hours

Job summary

Annapurna Labs (U.S.) Inc. is seeking an ASIC Design Engineer to design and optimize hardware for AWS data centers, including AWS Inferentia. You will develop high-performance, power-efficient RTL and collaborate with cross-functional teams to ensure quality and timely delivery.

The role requires a strong SystemVerilog background, knowledge of microarchitectures, and experience with RTL synthesis and timing constraints. Competitive base salary and comprehensive benefits are provided.

Qualifications

• Bachelor's degree or equivalent in a relevant field.
• 3+ years of non-internship design or architecture experience on new or existing systems.
• 3+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience.

Responsibilities

• Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets.
• Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements.
• Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints.
• Execute lint and clock domain crossing quality checks to ensure design integrity.

Skills

SystemVerilog

RTL design

Digital design

Analytical problem solving

Education

Bachelor's degree or equivalent

Master's degree in computer science or equivalent

Tools

Synthesis

Timing analysis

Job description

Annapurna Labs (U.S.) Inc. is seeking an ASIC Design Engineer to design and optimize hardware for AWS data centers, including AWS Inferentia. You will develop high-performance, power-efficient RTL and collaborate with cross-functional teams to ensure quality and timely delivery.

The role requires a strong SystemVerilog background, knowledge of microarchitectures, and experience with RTL synthesis and timing constraints. Competitive base salary and comprehensive benefits are provided.