ASIC Engineer I: RTL, SoC Design for ML Accelerators

Amazon; Austin (TX); On-site; USD 116,000 - 134,000; Full time

Benefits offered by this job

EAP

Mental Health Support

Medical Advice Line

401(k) matching

Job summary

Annapurna Labs (U.S.) Inc. invites engineering interns to contribute to real chip development work for the ASIC team. You will design RTL blocks, verify designs, and participate in the silicon implementation process under guidance from seasoned engineers.

The role emphasizes hands-on learning from day one, collaboration across teams, and exposure to EDA tools in a fast-paced environment, with opportunities to shape hardware products used broadly.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science with expected graduation May 2027 or earlier.
• Experience or coursework in digital logic design and computer architecture.
• Familiarity with Verilog/SystemVerilog or VHDL.
• Understanding of digital design concepts: combinational/sequential logic, FSMs, timing and clocking.

Responsibilities

• Design and implement RTL for digital logic blocks using Verilog/SystemVerilog.
• Develop and run verification environments to validate design functionality and coverage.
• Support synthesis, timing analysis, and physical design flows.
• Debug design issues through simulation and analysis.
• Collaborate with architecture, verification, and physical design teams to take features from specification to silicon.
• Document design decisions and present work to the team.

Skills

RTL design

Verilog/SystemVerilog

Digital design concepts

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Cadence tools

Synopsys tools

Python scripting

Job description

Annapurna Labs (U.S.) Inc. invites engineering interns to contribute to real chip development work for the ASIC team. You will design RTL blocks, verify designs, and participate in the silicon implementation process under guidance from seasoned engineers.

The role emphasizes hands-on learning from day one, collaboration across teams, and exposure to EDA tools in a fast-paced environment, with opportunities to shape hardware products used broadly.