Senior ASIC Design Engineer for ML Inference SoCs

Annapurna Labs; Austin (TX); Presencial; USD 154.000 - 215.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Health insurance

401(k) matching

Paid time off

Parental leave

Descripción de la vacante

Annapurna Labs in Austin, TX seeks an ASIC Design Engineer to drive high-performance, area- and power-efficient SystemVerilog RTL designs for AWS machine learning servers.

You will analyze microarchitectures, deliver synthesis-ready designs, and collaborate with architects, verification, and back-end teams to optimize features, power, and performance while ensuring design integrity through lint and clock domain crossing checks.

Formación

• Bachelor's degree or equivalent
• 3+ years of non-internship design or architecture (design patterns, reliability and scaling) of new and existing systems experience
• Master's degree in computer science or equivalent is preferred and 3+ years of full software development lifecycle experience is desirable

Responsabilidades

• Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets
• Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements
• Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints
• Execute lint and clock domain crossing quality checks to ensure design integrity
• Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts

Conocimientos

SystemVerilog

ASIC design

RTL design

Performance optimization

Clock domain crossing

Educación

Bachelor's degree

Master's degree

Descripción del empleo

Annapurna Labs in Austin, TX seeks an ASIC Design Engineer to drive high-performance, area- and power-efficient SystemVerilog RTL designs for AWS machine learning servers.

You will analyze microarchitectures, deliver synthesis-ready designs, and collaborate with architects, verification, and back-end teams to optimize features, power, and performance while ensuring design integrity through lint and clock domain crossing checks.