Lead ASIC Designer for Cloud-Scale ML Acceleration

Annapurna Labs

San Diego (CA)

Presencial

USD 213.000 - 288.000

Jornada completa

hace 32 horas
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Descripción de la vacante

Annapurna Labs (U.S.) Inc. in Cupertino, CA is seeking an ASIC Design Engineer to design and optimize custom silicon for AWS ML servers. You will implement high-performance RTL, collaborate with cross-functional teams, and ensure power-efficient solutions in a large-scale data-center environment.

The role requires a Bachelor's in Electrical Engineering with 5+ years in RTL/VLSI, and prefers a master's. You will contribute to architecture decisions and deliver robust, scalable designs in

Formación

  • BS in Electrical Engineering or related field required.
  • 5+ years RTL design for SOC and 5+ years VLSI engineering experience.
  • Experience with code quality tools (Spyglass, LINT, CDC).

Responsabilidades

  • Integrate multiple subsystems into top level SOC with clock/reset/DFT routing.
  • Implement high performance RTL to meet design targets and specs.
  • Analyze design decisions for power, performance or area trade-offs.
  • Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis-ready designs.
  • Perform lint and clock domain crossing quality checks.
  • Collaborate with architects, verification, pre-/ post-silicon teams to complete tasks.

Conocimientos

RTL design
VLSI engineering
Code quality tools
Scripting for automation

Educación

Bachelor's in Electrical Engineering
Master's or PhD in Electrical Engineering (preferred)

Herramientas

SystemVerilog
CDC
Spyglass/LINT

Descripción del empleo

Annapurna Labs (U.S.) Inc. in Cupertino, CA is seeking an ASIC Design Engineer to design and optimize custom silicon for AWS ML servers. You will implement high-performance RTL, collaborate with cross-functional teams, and ensure power-efficient solutions in a large-scale data-center environment.

The role requires a Bachelor's in Electrical Engineering with 5+ years in RTL/VLSI, and prefers a master's. You will contribute to architecture decisions and deliver robust, scalable designs in

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