Senior ASIC Design Engineer — Cloud-Scale ML Acceleration

Amazon Inc.; Austin (TX); On-site; USD 213,000 - 288,000; Full time

Job summary

Amazon Web Services (AWS) is seeking an ASIC Design Engineer to join the Cloud-Scale Machine Learning Acceleration team in Cupertino, CA. You will design and optimize RTL for SOCs, integrate subsystems, and deliver high-performance, power-efficient hardware for AWS Inferentia.

You will work with architects, verification, and back-end teams; qualifications include 5+ years RTL/VLSI, experience with Spyglass/LINT/CDC, and proficiency in SystemVerilog and Python.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• 5+ years in RTL design for SOC and 5+ years in VLSI engineering.
• 5+ years with code quality tools including Spyglass, LINT, or CDC.
• Experience with SystemVerilog RTL, assertions and timing constraints.

Responsibilities

• Implement and deliver high performance, area and power efficient RTL.
• Integrate subsystems into top level SOC with proper clock/reset routing.
• Analyze design choices comparing features, power, performance, and area.
• Develop micro-architecture and deliver synthesis/timing clean designs.
• Perform lint and clock domain crossing quality checks.
• Collaborate with architects, verification, and back-end teams to complete tasks.

Skills

RTL design for SOC

VLSI engineering

Python scripting

Assertions

Debugging RTL

Education

Bachelor's degree in Electrical Engineering or a related field

Tools

SystemVerilog

Spyglass

LINT

CDC

Job description

Amazon Web Services (AWS) is seeking an ASIC Design Engineer to join the Cloud-Scale Machine Learning Acceleration team in Cupertino, CA. You will design and optimize RTL for SOCs, integrate subsystems, and deliver high-performance, power-efficient hardware for AWS Inferentia.

You will work with architects, verification, and back-end teams; qualifications include 5+ years RTL/VLSI, experience with Spyglass/LINT/CDC, and proficiency in SystemVerilog and Python.