Senior STA Engineer – Low-Power SoC Timing & Synthesis

Qualcomm; Santa Clara (CA); On-site; USD 153,200 - 229,800; Full time

Job summary

Qualcomm Atheros, Inc. is seeking a senior role focused on static timing analysis, synthesis, and low‑power implementation for complex WiFi SoCs.

The position requires hands‑on experience with PrimeTime, Design Compiler, Genus, and multi‑corner/multi‑mode timing closure, working with RTL, synthesis, and physical design teams in a dynamic environment. Responsibilities include driving subsystem timing closure, developing SDC constraints, and optimizing I/O budgets, while implementing AI‑driven

Qualifications

• 6–8 years of experience in ASIC/SoC STA, synthesis, and timing constraint development.
• Deep knowledge of Static Timing Analysis (STA) and timing constraints.
• Experience with MMMC timing closure, OCV/AOCV/POCV, and advanced tech nodes.
• Experience in synthesis and LEC (RTL‑to‑Netlist and Netlist‑to‑Netlist).
• Understanding SOC clocking and reset methodology and implementation.
• Scripting skills in TCL and Perl.
• Exposure to low‑implementation techniques and UPF multi‑voltage checks.
• Hands‑on with PrimeTime, Design Compiler, and Cadence Genus.

Responsibilities

• Timing Analysis: drive STA and tight timing closure for pre‑layout and post‑layout.
• Use PrimeTime or equivalents and contribute to full‑chip signoff.
• Identify bottlenecks, debug violations, and suggest optimizations.
• Develop and validate SDC constraints (MMMC setup) to enable STA accuracy.
• Define I/O timing budgets across designs and provide root‑cause analysis.
• Manage large multi‑corner/multi‑mode STA runs with automation.
• Collaborate with RTL, synthesis, and physical design for robust closure.
• Synthesis & Implementation: perform synthesis (low power), LEC, and ECOs.
• Validate QoR and handoff to physical design; maintain SDC constraints.
• Balance PPA across implementation; perform Conformal ECOs as needed.
• Methodology: develop AI‑driven flows using TCL, Perl, and Python.

Skills

STA expertise

Multi‑Corner MMMC

Scripting TCL/Perl

Python scripting

Synthesis

LEC

SOC clocking

UPF/multi‑voltage checks

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

PrimeTime

Design Compiler

Cadence Genus

Job description

Qualcomm Atheros, Inc. is seeking a senior role focused on static timing analysis, synthesis, and low‑power implementation for complex WiFi SoCs.

The position requires hands‑on experience with PrimeTime, Design Compiler, Genus, and multi‑corner/multi‑mode timing closure, working with RTL, synthesis, and physical design teams in a dynamic environment. Responsibilities include driving subsystem timing closure, developing SDC constraints, and optimizing I/O budgets, while implementing AI‑driven