Lead ASIC Design Architect - High-Performance Networking

Hewlett Packard Enterprise Company; Roseville (CA); On-site; USD 174,000 - 353,000; Full time

Job summary

Hewlett Packard Enterprise in California seeks a Senior Principal ASIC Design Engineer to lead high-speed networking silicon from concept to tape-out.

You will work with product marketing, hardware, software, verification, and physical design teams to optimize power, performance, and area while driving design methodologies and AI-assisted flows.

The role requires 15+ years of ASIC experience, strong leadership, and deep expertise in Verilog/SystemVerilog, Synthesis, and modern EDA tooling.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 15+ years of relevant ASIC design experience.
• Strong coding in Verilog and SystemVerilog.
• Experience with AI-assisted design methodologies preferred.

Responsibilities

• Lead a significant ASIC subsystem from architecture to netlist.
• Collaborate with cross-functional teams to meet power, area, and timing goals.
• Develop RTL and verification components, including assertions.
• Mentor engineers and advance design methodologies.

Skills

Verilog

SystemVerilog

ASIC design

Power optimization

Python

Perl

AI-assisted design

Leadership

Education

Bachelor's degree in Electrical Engineering

Master's degree preferred

Tools

Synthesis tools

EDA tools

Job description

Hewlett Packard Enterprise in California seeks a Senior Principal ASIC Design Engineer to lead high-speed networking silicon from concept to tape-out.

You will work with product marketing, hardware, software, verification, and physical design teams to optimize power, performance, and area while driving design methodologies and AI-assisted flows.

The role requires 15+ years of ASIC experience, strong leadership, and deep expertise in Verilog/SystemVerilog, Synthesis, and modern EDA tooling.