Senior Principal ASIC Design Lead — Networking

Hewlett Packard Enterprise; Roseville (CA); Vor Ort; USD 174.000 - 353.000; Vollzeit

Zusammenfassung

Hewlett Packard Enterprise Development LP is seeking a Senior Principal ASIC Design Engineer to lead high‑performance networking ASIC subsystems from architecture through tape‑out. Based in California, you will collaborate with cross‑functional teams to meet power, area, and timing targets while driving design methodology innovations.

The role emphasizes technical leadership, deep Verilog/SystemVerilog expertise, and experience with cutting‑edge AI-augmented design practices.

Qualifikationen

• 15+ years of ASIC design experience.
• Bachelor’s degree in Electrical Engineering or related field; Master’s preferred.
• First-authored patents in networking or computer architecture is a plus.

Aufgaben

• Define architecture for a significant ASIC subsystem and translate requirements into a detailed specification.
• Collaborate with product marketing, hardware, software, verification, and physical design teams to meet power, area, and timing goals.
• Write functional and micro-architecture specifications for modules and subsystems.
• Implement RTL modules using Verilog/SystemVerilog with emphasis on quality and timing.
• Develop functional coverage and SystemVerilog Assertions to improve verification quality.
• Apply power-reduction techniques to meet aggressive power targets.
• Coordinate with physical design for floorplanning and timing closure.
• Work with verification to ensure full validation against requirements.
• Provide technical leadership and mentoring across the design team.
• Drive automation, AI-assisted design methods, and advanced EDA workflows.

Kenntnisse

ASIC architecture

Verilog

SystemVerilog

Technical leadership

Python

Perl

Ausbildung

Bachelor’s degree in Electrical Engineering or related field

Master’s degree preferred

Tools

Synthesis tools

Lint/CDC/Formal

AI automation frameworks

Jobbeschreibung

Hewlett Packard Enterprise Development LP is seeking a Senior Principal ASIC Design Engineer to lead high‑performance networking ASIC subsystems from architecture through tape‑out. Based in California, you will collaborate with cross‑functional teams to meet power, area, and timing targets while driving design methodology innovations.

The role emphasizes technical leadership, deep Verilog/SystemVerilog expertise, and experience with cutting‑edge AI-augmented design practices.