Senior ASIC Design Engineer - High-Speed Optics & DSP

Celero Communications, Inc.; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. is seeking an experienced ASIC Design Engineer to develop high-speed digital blocks for optical communication systems.

The candidate will own RTL/ASIC blocks and collaborate across DSP, SerDes, Analog, and Verification teams to meet stringent performance, power, and area targets. Ideal candidates have extensive Verilog/SystemVerilog experience, strong DSP/SerDes knowledge, and a track record delivering complex silicon from RTL through tapeout, with hands-on

Qualifications

• Master’s or Ph.D. in Electrical/Electrical Engineering or related field.
• 10+ years in digital ASIC design with ownership of blocks/subsystems.
• Proficient in Verilog or SystemVerilog and RTL design.
• Strong understanding of digital design, RTL, and ASIC workflows.
• Experience with ASIC design flows and industry-standard EDA tools.
• Knowledge of DSP, high-speed SerDes, analog/mixed-signal ICs, and optical comms.
• Experience with synthesis, STA, lint, CDC, formal verification, and RTL sim.
• Familiar with UVM or formal verification and low-power PPA techniques.
• Analytical, problem-solving, and effective team collaboration.

Responsibilities

• Design and implement high-performance digital circuits and ASIC blocks in Verilog/SystemVerilog.
• Develop DSP, digital comms, and high-speed SerDes in complex ASICs.
• Collaborate with Analog/SerDes/DSP/Verification teams for mixed-signal integration.
• Develop high-speed data paths, control logic, and interfaces for optical systems.
• Perform synthesis, timing, lint, CDC, and signoff activities for ASICs.
• Optimize designs for performance, power, and area (PPA).
• Run RTL simulations and debugging; support silicon bring-up.
• Contribute to architecture reviews and mentor engineers.
• Create scripts (Python/Tcl) to automate design/verification tasks.

Skills

Verilog/SystemVerilog

DSP

High-speed SerDes

Digital/Silicon Design

RTL Design

C/Python scripting

Education

Master’s or Ph.D. in Electrical Engineering or Computer Engineering

Tools

EDA tools

Job description

Celero Communications, Inc. is seeking an experienced ASIC Design Engineer to develop high-speed digital blocks for optical communication systems.

The candidate will own RTL/ASIC blocks and collaborate across DSP, SerDes, Analog, and Verification teams to meet stringent performance, power, and area targets. Ideal candidates have extensive Verilog/SystemVerilog experience, strong DSP/SerDes knowledge, and a track record delivering complex silicon from RTL through tapeout, with hands-on