Senior ASIC Design Engineer - DSP/Analog/SerDes

Celero Communications, Inc.; San Jose (CA); Presencial; USD 150 000 - 250 000; Tempo integral

Resumo da oferta

Celero Communications, Inc. is seeking an experienced ASIC Design Engineer to develop high-speed digital blocks for optical communication systems.

The candidate will own RTL/ASIC blocks and collaborate across DSP, SerDes, Analog, and Verification teams to meet stringent performance, power, and area targets. Ideal candidates have extensive Verilog/SystemVerilog experience, strong DSP/SerDes knowledge, and a track record delivering complex silicon from RTL through tapeout, with hands-on

Qualificações

• Master’s or Ph.D. in Electrical/Electrical Engineering or related field.
• 10+ years in digital ASIC design with ownership of blocks/subsystems.
• Proficient in Verilog or SystemVerilog and RTL design.
• Strong understanding of digital design, RTL, and ASIC workflows.
• Experience with ASIC design flows and industry-standard EDA tools.
• Knowledge of DSP, high-speed SerDes, analog/mixed-signal ICs, and optical comms.
• Experience with synthesis, STA, lint, CDC, formal verification, and RTL sim.
• Familiar with UVM or formal verification and low-power PPA techniques.
• Analytical, problem-solving, and effective team collaboration.

Responsabilidades

• Design and implement high-performance digital circuits and ASIC blocks in Verilog/SystemVerilog.
• Develop DSP, digital comms, and high-speed SerDes in complex ASICs.
• Collaborate with Analog/SerDes/DSP/Verification teams for mixed-signal integration.
• Develop high-speed data paths, control logic, and interfaces for optical systems.
• Perform synthesis, timing, lint, CDC, and signoff activities for ASICs.
• Optimize designs for performance, power, and area (PPA).
• Run RTL simulations and debugging; support silicon bring-up.
• Contribute to architecture reviews and mentor engineers.
• Create scripts (Python/Tcl) to automate design/verification tasks.

Conhecimentos

Verilog/SystemVerilog

DSP

High-speed SerDes

Digital/Silicon Design

RTL Design

C/Python scripting

Formação académica

Master’s or Ph.D. in Electrical Engineering or Computer Engineering

Ferramentas

EDA tools

Descrição da oferta de emprego

San Jose, CA

Celero Communications is an exciting and fast-growing semiconductor startup developing innovative technologies that power next-generation AI and data center infrastructure. Our products enable high-performance optical connectivity and next-generation optical transceivers and modems. Celero is seeking a highly skilled and motivated ASIC Design Engineer to join our team and contribute to the development of advanced ASICs for high-speed optical communication systems. The ideal candidate will have strong digital ASIC design expertise combined with hands-on experience in DSP, Analog, and/or SerDes technologies.

Duties & Responsibilities

• Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.
• Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs.
• Work closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs.
• Participate in the design and development of high-speed data paths, signal processing blocks, control logic, and interfaces for optical communication systems.
• Perform synthesis, timing analysis, lint, formal equivalence, Clock Domain Crossing (CDC), and related ASIC implementation and signoff activities.
• Optimize designs for performance, power, and area (PPA).
• Perform RTL simulation and debugging to ensure design functionality and performance.
• Contribute to block-level and top-level integration, verification, and silicon bring-up.
• Participate in architecture and design reviews and provide technical guidance to other engineers.
• Collaborate with cross-functional teams to troubleshoot complex design and system-level issues.
• Develop scripts and automation using Python, Tcl, or similar languages to improve design and verification efficiency.
• Contribute to ASIC development from architecture and RTL through tapeout and silicon validation.

Required Qualifications

• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.
• 10+ years of experience in digital ASIC design, with demonstrated ownership of complex ASIC blocks or subsystems.
• Strong proficiency in Verilog and/or SystemVerilog.
• Strong understanding of digital design principles, RTL design, and ASIC development methodologies.
• Hands-on experience with ASIC design flows and industry-standard EDA tools.
• Strong knowledge of one or more of the following areas:
• Digital Signal Processing (DSP)
• High-speed SerDes
• Analog/Mixed-Signal ICs
• Digital communications
• Optical communications
• Experience working with DSP algorithms, data-path architectures, FEC, equalization, modulation/demodulation, or other high-speed communication technologies.
• Understanding of SerDes architectures and high-speed interfaces, including TX/RX datapaths, equalization, clocking, and related mixed-signal interfaces.
• Experience collaborating with Analog and Mixed-Signal design teams and understanding the interaction between digital, analog, and SerDes blocks.
• Experience with synthesis, static timing analysis, Lint, CDC, formal verification, and RTL simulation.
• Familiarity with verification methodologies such as UVM and/or formal verification.
• Knowledge of low-power design techniques and PPA optimization.
• Strong analytical and problem-solving skills.
• Excellent communication and teamwork skills with the ability to work effectively in a fast-paced startup environment.

Preferred Qualifications

• Experience designing ASICs for optical communications, optical transceivers, coherent communications, or high-speed networking.
• Experience with coherent DSP, FEC, modulation schemes, equalization, or high-speed data recovery.
• Experience with SerDes architectures, including TX/RX, CDR, PLLs, CTLE, DFE, ADC/DAC interfaces, or related high-speed mixed-signal circuitry.
• Experience working with advanced semiconductor process technologies.
• Experience taking ASICs from architecture/RTL through synthesis, physical implementation, tapeout, and silicon bring-up.
• Experience with MATLAB, Python, Tcl, or other modeling and automation tools.
• Understanding of optical communication standards and high-speed networking protocols.
• Experience working in a startup or fast-paced semiconductor development environment.

Why Join Celero?

At Celero, you will have the opportunity to work on challenging, high-performance semiconductor technologies at the intersection of AI infrastructure, optical communications, DSP, SerDes, and mixed-signal design. You will work closely with experienced engineers across multiple disciplines and have the opportunity to make significant contributions to products from architecture through silicon.

Annual Base Salary Range for US: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

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As set forth in Celero Communications, Inc.’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

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An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.