Senior ASIC Design Engineer – Optics & High-Speed SoCs

Ayar Labs, Inc.; San Jose (CA); On-site; USD 180,000 - 223,000; Full time

Job summary

Ayar Labs is seeking an ASIC Sr. Staff Engineer to lead design, bring-up and debug of complex digital subsystems in an electro-optical SoC. You will work in a small IC design team, hands-on and independent, delivering clear specifications and robust RTL.

You will collaborate with analog, photonics and firmware engineers, develop testbenches, verify with XCelium/VCS/Questa, and drive timing signoff across multiple clock domains in high‑speed interconnects and optics.

Qualifications

• BS in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of work or academic experience in ASIC design.
• Mastery of Verilog and SystemVerilog for RTL and verification.
• Proficient in ASIC verification tools (XCelium, VCS, Questa).
• Proficient in C/C++ and Python.
• Experience with SOC interconnect fabrics (AXI/AHB/APB) and multiple clock domains.

Responsibilities

• Develop detailed digital algorithm specifications with analog, photonics, and firmware engineers.
• Develop and optimize RTL in Verilog for electro-optical ASICs.
• Create models and testbenches for digital and mixed-signal blocks.
• Document designs to enable backend ASIC timing signoff.
• Bringup, evaluation, and debug of in-house silicon using scripting and firmware.
• Contribute to automated design methodologies and flows.

Skills

Verilog

SystemVerilog

C/C++

Python

ASIC verification

AMBA AXI/AHB/APB

Clock domains

HDL Simulation

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree (preferred)

Tools

XCelium

VCS

Questa

Genus/Design Compiler (preferred)

Job description

Ayar Labs is seeking an ASIC Sr. Staff Engineer to lead design, bring-up and debug of complex digital subsystems in an electro-optical SoC. You will work in a small IC design team, hands-on and independent, delivering clear specifications and robust RTL.

You will collaborate with analog, photonics and firmware engineers, develop testbenches, verify with XCelium/VCS/Questa, and drive timing signoff across multiple clock domains in high‑speed interconnects and optics.