Senior ASIC Design Engineer - High-Speed Optical DSP

Celero Communications, Inc.; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. in Irvine, CA seeks an experienced ASIC Design Engineer to develop high-speed digital blocks for optical communication systems. You will lead RTL design, Verilog/SystemVerilog, and work with DSP, SerDes, and mixed-signal teams from architecture through silicon bring-up.

The role emphasizes performance, power, and area optimization, synthesis and verification using industry-standard EDA tools, and scripting in Python or Tcl to automate flows. A Master’s or Ph.D.

Qualifications

• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.
• 10+ years of experience in digital ASIC design with ownership of complex blocks/subsystems.
• Strong proficiency in Verilog and/or SystemVerilog.
• Strong understanding of digital design principles, RTL design, and ASIC development methodologies.
• Hands-on experience with ASIC design flows and industry-standard EDA tools.
• Experience in DSP, high-speed SerDes, analog/mixed-signal ICs, digital communications, or optical communications.

Responsibilities

• Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.
• Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs.
• Collaborate with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop mixed-signal ASICs.
• Work on high-speed data paths, signal processing blocks, control logic, and interfaces for optical systems.
• Perform synthesis, timing analysis, lint, formal equivalence, CDC, and related ASIC signoff activities.
• Optimize designs for performance, power, and area (PPA).
• Perform RTL simulation and debugging to ensure design functionality.
• Contribute to block/top-level integration, verification, and silicon bring-up.
• Participate in architecture/design reviews and provide guidance to engineers.
• Collaborate with cross-functional teams to troubleshoot design and system issues.
• Develop scripts and automation using Python, Tcl, or similar languages.
• Contribute to ASIC development from architecture/RTL through tapeout and silicon validation.

Skills

Verilog/SystemVerilog

Digital ASIC design

DSP

High‑speed SerDes

RTL design

ASIC design flows

Scripting (Python/Tcl)

Education

Master’s or Ph.D. in Electrical Engineering or related field

Tools

EDA tools

Job description

Celero Communications, Inc. in Irvine, CA seeks an experienced ASIC Design Engineer to develop high-speed digital blocks for optical communication systems. You will lead RTL design, Verilog/SystemVerilog, and work with DSP, SerDes, and mixed-signal teams from architecture through silicon bring-up.

The role emphasizes performance, power, and area optimization, synthesis and verification using industry-standard EDA tools, and scripting in Python or Tcl to automate flows. A Master’s or Ph.D.