Senior ASIC Design Engineer — DSP/SerDes/Analog

Celero Communications, Inc.; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. is seeking an ASIC Design Engineer to drive DSP, SerDes, and mixed-signal integration for high-speed optical systems.

The role requires 5+ years in digital ASIC design, proficiency in Verilog/SystemVerilog, and hands-on experience with EDA tools. You will collaborate across architecture, verification, and physical design while optimizing for performance and power in a fast-paced startup.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field is required.
• 5+ years of experience in digital ASIC design with ownership of complex blocks or subsystems.
• Proficiency in Verilog and SystemVerilog; strong RTL design fundamentals.

Responsibilities

• Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.
• Develop DSP, digital communication, and high-speed SerDes functionality into ASIC designs.
• Collaborate with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams.

Skills

Verilog/SystemVerilog

DSP

SerDes

RTL design

Python/Tcl scripting

FPGA/ASIC flows

Low-power design

Problem solving

Team collaboration

Education

Bachelor’s degree in Electrical Engineering or related field

Tools

EDA tools

Job description

Celero Communications, Inc. is seeking an ASIC Design Engineer to drive DSP, SerDes, and mixed-signal integration for high-speed optical systems.

The role requires 5+ years in digital ASIC design, proficiency in Verilog/SystemVerilog, and hands-on experience with EDA tools. You will collaborate across architecture, verification, and physical design while optimizing for performance and power in a fast-paced startup.