Senior Analog Design Engineer - High-Speed AI Transceivers

Celero Communications, Inc.; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. in Irvine, CA is seeking an experienced Analog Design Engineer to architect and deliver high-performance analog and mixed-signal circuits for next-generation transceivers.

You will contribute from architecture to silicon, collaborating with a world-class team on advanced process nodes. The ideal candidate has a Master’s or PhD in EE with 5+ years in analog design, strong layout awareness, and proficiency with Virtuoso/Spectre/ADE.

Qualifications

• Master’s degree and/or PhD in Electrical Engineering or related field with 5+ years of experience.
• Strong analog design fundamentals and experience with broadband amplification, clock generation, and/or fundamental analog blocks.
• Experience with analog design and verification tools (Virtuoso, Spectre, ADE, post layout extraction).
• Experience in advance CMOS design/verification flows and electromigration/SOA evaluation.
• Familiarity with EM simulation tools is a plus; solid understanding of FinFET analog layouts.

Responsibilities

• Design high-speed analog circuits for transceivers and related high-speed functions.
• Architect, design, and deliver analog/mixed-signal circuits from architecture to silicon.
• Oversee analog layouts within advanced process nodes and verify design specs.
• Support silicon bring-up, debugging, and documentation; collaborate across teams.

Skills

Analog design fundamentals

High-speed circuit design

Clock generation and distribution

CMOS design & verification flows

RF/mixed-signal design

Documentation & communication

Education

Master’s degree and/or PhD in Electrical Engineering

Tools

Virtuoso

Spectre

ADE

Post layout extraction tools

EM/EMX, Momentum, HFSS

Job description

Celero Communications, Inc. in Irvine, CA is seeking an experienced Analog Design Engineer to architect and deliver high-performance analog and mixed-signal circuits for next-generation transceivers.

You will contribute from architecture to silicon, collaborating with a world-class team on advanced process nodes. The ideal candidate has a Master’s or PhD in EE with 5+ years in analog design, strong layout awareness, and proficiency with Virtuoso/Spectre/ADE.