Senior ASIC Design Engineer - High-Speed Networking Remote

Cornelis Networks, Inc.; Austin (TX); Remote; USD 150,000 - 230,000; Full time

Benefits offered by this job

Equity

Health benefits

401(k)

Job summary

Cornelis Networks, Inc. is seeking Senior ASIC Design Engineers to develop world-class SoCs for AI and HPC interconnects.

You will design RTL in Verilog/SystemVerilog, drive timing closure with Physical Design, and work across hardware, firmware, and software teams to deliver scalable, high-performance networking solutions. Ideal candidates have 8+ years in digital ASIC design, expertise in Ethernet protocols (50G/100G/400G), and experience with RTL verification, debugging, and scripting.

Qualifications

• 8+ years of post-college experience in digital design.
• Experience in RTL design for high-speed data paths or ASIC packet processing.
• Deep understanding of Host Ethernet adaptor architectures.

Responsibilities

• Implement RTL designs using Verilog/SystemVerilog for high-speed data paths and packet processing.
• Collaborate with verification engineers to create block- and system-level test plans.
• Define timing constraints for RTL blocks and work with Physical Design to optimize timing closure.
• Support post-silicon validation with hardware, firmware, and software teams to debug ASIC issues.
• Contribute to performance optimization and power-aware design strategies for Host Fabric Interface subsystems.

Skills

Verilog

SystemVerilog

Education

B.S./M.S. in Computer or Electrical Engineering

Tools

Design Compiler

Spyglass

PrimeTime

Job description

Cornelis Networks, Inc. is seeking Senior ASIC Design Engineers to develop world-class SoCs for AI and HPC interconnects.

You will design RTL in Verilog/SystemVerilog, drive timing closure with Physical Design, and work across hardware, firmware, and software teams to deliver scalable, high-performance networking solutions. Ideal candidates have 8+ years in digital ASIC design, expertise in Ethernet protocols (50G/100G/400G), and experience with RTL verification, debugging, and scripting.