Remote Senior ASIC Design Leader: RTL & SoC Execution

cornelisnetworks; San Jose (CA); On-site; USD 210,000 - 320,000; Full time

Benefits offered by this job

Equity

Health benefits

401(k) with company match

Open Time Off

Job summary

Cornelis Networks is seeking a Senior ASIC Design Engineering Manager to lead and grow our RTL design team. Reporting to the VP of ASIC Engineering, you will manage a world-class group across full lifecycle of next-gen high-performance networking ASICs, from microarchitecture to tape-out, with cross-functional collaboration among Architecture, Verification, Emulation, and Physical Design.

You will drive schedules, resource planning, and headcount strategy in a remote-capable environment,

Qualifications

• 15+ years in the semiconductor industry with leadership experience.
• At least 5 years in people management and building large engineering teams.
• Deep understanding of interaction between Design, Verification, Emulation and Physical Design teams.

Responsibilities

• Own RTL delivery schedules across major milestones and track progress.
• Predict scheduler risks and reallocate resources to stay on track.
• Align RTL delivery with DV/Emulation enablement and manage dependencies.
• Lead physical design handoffs with high-quality RTL and constraints to minimize timing iterations.
• Lead long-term headcount planning and organizational design for the ASIC department.
• Optimize designs for PPA and integrate major subsystems like interconnect and memory.

Skills

RTL design

Verilog/SystemVerilog

Synthesis

STA/timing closure

Physical design

Verification methodologies

Microarchitecture development

Leadership

People management

SoC flows

Education

B.S./M.S. in Computer or Electrical Engineering

Tools

Emulation

Job description

Cornelis Networks is seeking a Senior ASIC Design Engineering Manager to lead and grow our RTL design team. Reporting to the VP of ASIC Engineering, you will manage a world-class group across full lifecycle of next-gen high-performance networking ASICs, from microarchitecture to tape-out, with cross-functional collaboration among Architecture, Verification, Emulation, and Physical Design.

You will drive schedules, resource planning, and headcount strategy in a remote-capable environment,