Remote Senior ASIC Design Leader — RTL/SoC Excellence

Cornelis Networks; San Jose (CA); On-site; USD 180,000 - 280,000; Full time

Benefits offered by this job

Equity

Health insurance

401(k) match

Paid holidays

Job summary

Cornelis Networks is seeking a Senior ASIC Design Engineering Manager to lead our RTL design team through full lifecycle development of high-performance networking ASICs. You will report to the VP of ASIC Engineering and drive schedules, resource alignment, and cross-functional collaboration across Architecture, Design Verification, Emulation, and Physical Design.

You will own headcount planning and organizational design, with exposure to AI-based design flows.

Qualifications

• 15+ years in semiconductor industry with high performance designs
• 5+ years in people management
• Experience leading full-cycle ASIC product launches
• Knowledge of RTL, verification, emulation, and physical design interactions
• Exposure to PCIe, Ethernet, UCIe, or UALink is a plus

Responsibilities

• Own ASIC RTL delivery across major milestones
• Use data-driven insights to predict schedule risks
• Align RTL with DV and emulation enablement
• Lead physical design handoffs and tape-out milestones
• Headcount planning and global talent acquisition

Skills

RTL design

Verilog

SystemVerilog

Synthesis

STA/timing

Physical design

Verification methodologies

Microarchitecture

Leadership

Program management

Remote leadership

Education

B.S./M.S. in C.E. or E.E.

Tools

None specified

Job description

Cornelis Networks is seeking a Senior ASIC Design Engineering Manager to lead our RTL design team through full lifecycle development of high-performance networking ASICs. You will report to the VP of ASIC Engineering and drive schedules, resource alignment, and cross-functional collaboration across Architecture, Design Verification, Emulation, and Physical Design.

You will own headcount planning and organizational design, with exposure to AI-based design flows.