Senior PCIe ASIC Design Lead — Remote

Cornelis Networks, Inc.; Austin (TX); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Equity

Cash incentives

Health benefits

Retirement plan

Job summary

Cornelis Networks is hiring a Senior ASIC Design Engineer to lead PCIe controller integration into next-generation SoCs. You will drive end-to-end PCIe IP integration, collaborate across architecture, verification, physical design, and software teams, and oversee silicon bring-up and validation.

The ideal candidate has 10+ years in ASIC/SoC design, deep PCIe protocol knowledge, lab experience, and strong scripting and communication skills. Remote role within the US with strong total rewards.

Qualifications

• BS/MS in Electrical Engineering or related field.
• 10+ years in ASIC/SoC design with a focus on PCIe controller integration.
• Proven silicon bring-up and debug of high-speed interfaces.
• Strong PCIe protocol knowledge (PHY, MAC, TLP, DLL) and interoperability testing.
• Experience with verification tools and lab equipment such as oscilloscopes.
• Scripting skills in Python/Perl/TCL and strong communication abilities.

Responsibilities

• Own end-to-end integration of PCIe IP into complex ASIC designs.
• Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.
• Drive performance optimization across the PCIe stack, from PHY tuning to DMA/transaction layer efficiency.
• Lead silicon bring-up and validation of PCIe links in the lab; work with board and firmware teams.
• Provide mentorship and help define PCIe subsystem development best practices.

Skills

PCIe protocol

ASIC/SoC design

RTL bring-up & debug

Scripting (Python/Perl/TCL)

Communication skills

Lab equipment proficiency

Education

BS/MS in Electrical Engineering

Tools

VCS/Questa

Oscilloscopes

Protocol analyzers

Job description

Cornelis Networks is hiring a Senior ASIC Design Engineer to lead PCIe controller integration into next-generation SoCs. You will drive end-to-end PCIe IP integration, collaborate across architecture, verification, physical design, and software teams, and oversee silicon bring-up and validation.

The ideal candidate has 10+ years in ASIC/SoC design, deep PCIe protocol knowledge, lab experience, and strong scripting and communication skills. Remote role within the US with strong total rewards.