Remote Senior PCIe ASIC Design Engineer

Cornelis Networks; Austin (TX); On-site; USD 150,000 - 230,000; Full time

Benefits offered by this job

Equity

Bonus potential

Health benefits

401(k) with company match

Paid holidays

Open Time Off

Job summary

Cornelis Networks is hiring a Senior ASIC Design Engineer to lead PCIe controller integration into next-gen SoCs, driving IP bring-up and interconnect scalability. You will collaborate across architecture, verification, PD, and software teams to deliver robust PCIe subsystems.

The role emphasizes hands-on silicon bring-up, lab validation, and mentoring of junior engineers, with a strong focus on high-speed PCIe performance and protocol compliance. Remote-friendly in the U.S.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of industry experience in ASIC/SoC design with a focus on PCIe controller integration.
• Proven experience in silicon bring-up and debug of high-speed interfaces.
• Solid understanding of PCIe protocol stack (PHY, MAC, TLP, DLL), configuration space, and link training.
• Hands-on experience with PCIe verification environments, performance tuning, and power-aware design.
• Familiarity with PCIe compliance testing, simulation tools (e.g., VCS, Questa), and lab equipment (e.g., protocol analyzers, oscilloscopes).
• Strong scripting (Python, Perl, TCL) and debugging skills.
• Strong verbal and written communication skills.

Responsibilities

• Own end-to-end integration of PCIe IP into complex ASIC designs.
• Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.
• Drive performance optimization efforts across the PCIe stack, from PHY tuning to DMA/transaction layer efficiency.
• Contribute to system architecture and microarchitecture discussions with a focus on IO and interconnect scalability.
• Lead silicon bring-up and validation of PCIe links in the lab; work closely with board and firmware teams.
• Debug functional and performance issues at RTL, gate-level, and silicon.
• Ensure compliance with PCIe specifications and participate in interoperability testing where needed.
• Provide mentorship to junior engineers and help define PCIe subsystem development best practices.
• Good understanding of high-bandwidth, low-latency connectivity for high-performance compute platforms

Skills

ASIC/SoC design

PCIe controller integration

PCIe protocol

High-speed interfaces

Python/Perl/TCL

RTL/Debugging

Verilog

Lab equipment

PCIe verification

Debugging

Education

Electrical/Computer Eng degree

Tools

VCS/Questa

Emulation platforms (ZeBu, Palladium, HAPS)

Job description

Cornelis Networks is hiring a Senior ASIC Design Engineer to lead PCIe controller integration into next-gen SoCs, driving IP bring-up and interconnect scalability. You will collaborate across architecture, verification, PD, and software teams to deliver robust PCIe subsystems.

The role emphasizes hands-on silicon bring-up, lab validation, and mentoring of junior engineers, with a strong focus on high-speed PCIe performance and protocol compliance. Remote-friendly in the U.S.