Remote Senior ASIC RTL Design Leader

Cornelis Networks, Inc.; San Jose (CA); On-site; USD 260,000 - 360,000; Full time

Benefits offered by this job

Equity

Cash incentives

Annual bonuses

Health, dental, vision

401(k) with match

Open Time Off

Job summary

Cornelis Networks, Inc. is seeking a Senior ASIC Design Engineering Manager to lead and grow the RTL design team for next-generation high-performance networking ASICs.

Reporting to the VP of ASIC Engineering, you will manage a talented team and drive full-lifecycle RTL implementation, tape-out readiness, and cross-functional execution across Architecture, Design Verification, Emulation, and Physical Design.

Qualifications

• 15+ years in semiconductor industry with 5+ years in people management.
• Deep understanding of RTL, DV, emulation, and physical design coordination.
• Experience leading large teams through multiple ASIC launches in remote environments.
• Knowledge of PCIe, Ethernet, UCIe, UALink standards.

Responsibilities

• Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting progress against committed plans.
• Use data-driven insights to predict scheduler risks and reallocate resources to stay on track.
• Align RTL delivery with DV and emulation enablement and manage feedback loops and dependencies.
• Facilitate physical design handoffs with high-quality RTL and constraints to minimize timing-closure iterations.
• Lead long-term headcount planning and organizational design for the ASIC department; identify skill gaps and execute talent strategy.
• Demonstrate ability to optimize designs for PPA and integrate major subsystems (interconnect, I/O, memory).

Skills

People management

RTL design leadership

Verilog/SystemVerilog

Synthesis & timing closure

SoC integration

Education

B.S./M.S. in Computer/Electrical Engineering or related field

Job description

Cornelis Networks, Inc. is seeking a Senior ASIC Design Engineering Manager to lead and grow the RTL design team for next-generation high-performance networking ASICs.

Reporting to the VP of ASIC Engineering, you will manage a talented team and drive full-lifecycle RTL implementation, tape-out readiness, and cross-functional execution across Architecture, Design Verification, Emulation, and Physical Design.