Senior ASIC Design Engineer AI Networking & SoC

Advanced Micro Devices; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Benefits at a glance

Job summary

Advanced Micro Devices in Santa Clara, CA is seeking a Senior ASIC Design Engineer to lead high‑speed ASIC development from RTL architecture through tapeout and production. You will work across ASIC lifecycle with cross‑functional teams to deliver optimized networking and data‑movement blocks.

The role emphasizes collaboration, debug across multiple stages, and documentation. A strong background in Verilog/SystemVerilog, C/C++, Python, and networking is required.

Qualifications

• Experience in designing high-speed, complex ASICs.
• Hands-on RTL architecture to tapeout proficiency.
• Background in networking and packet processing.

Responsibilities

• Architect and design key blocks for next‑gen DPU ASICs targeting AI networking workloads.
• Contribute across the full ASIC development lifecycle.
• Collaborate on network processing engines including P4-based pipelines.
• Design and implement high‑speed ASIC blocks for networking and data movement.
• Work with verification, modeling, software, and hardware teams for correctness and performance.
• Debug across simulation, emulation, lab bring‑up, and post‑silicon phases.
• Contribute to performance, power, and area optimization.
• Assist integration of IPs into larger SoC architectures.
• Produce high‑quality design documentation and participate in reviews.

Skills

Verilog

SystemVerilog

C/C++

Python

RTL design

Networking ASICs

Collaboration

Debugging

Education

Bachelor/Master in EE

Job description

Advanced Micro Devices in Santa Clara, CA is seeking a Senior ASIC Design Engineer to lead high‑speed ASIC development from RTL architecture through tapeout and production. You will work across ASIC lifecycle with cross‑functional teams to deliver optimized networking and data‑movement blocks.

The role emphasizes collaboration, debug across multiple stages, and documentation. A strong background in Verilog/SystemVerilog, C/C++, Python, and networking is required.