Senior ASIC Design Lead - High-Performance Networking

Hewlett Packard Enterprise; Roseville (CA); On-site; USD 174,000 - 353,000; Full time

Job summary

Hewlett Packard Enterprise invites an experienced ASIC design engineer to lead a major subsystem within a high‑performance networking ASIC. You will translate product, hardware, and software requirements into a detailed subsystem specification and collaborate with product marketing, hardware, software, and verification teams.

You will drive RTL implementation, verification planning, and architectural trade‑offs, while mentoring engineers and advancing EDA flows and automation to improve design

Qualifications

• Bachelor’s degree in Electrical Engineering or related field required; Master’s degree preferred.
• 15+ years of relevant ASIC design experience.
• Strong analytical and technical decision‑making skills.
• Excellent written and verbal communication skills.

Responsibilities

• Serve as the technical lead for a significant subsystem within a high‑performance networking ASIC.
• Partner with cross‑functional teams to meet power, area, performance, timing and feature objectives.
• Author clear functional and micro‑architecture specifications for modules and subsystems.
• Implement RTL using Verilog/SystemVerilog with emphasis on quality and maintainability.
• Develop functional coverage and SystemVerilog Assertions for verification quality.
• Lead design methodologies, AI‑assisted flows, and automation to accelerate design closure.

Skills

ASIC design

Verilog/SystemVerilog

Technical leadership

Power optimization

Automation frameworks

Python

Perl

Education

Bachelor’s degree in Electrical Engineering or related field

Master’s degree preferred

Tools

Verilog

SystemVerilog

EDA tools

Scripting (Perl, Python)

Job description

Hewlett Packard Enterprise invites an experienced ASIC design engineer to lead a major subsystem within a high‑performance networking ASIC. You will translate product, hardware, and software requirements into a detailed subsystem specification and collaborate with product marketing, hardware, software, and verification teams.

You will drive RTL implementation, verification planning, and architectural trade‑offs, while mentoring engineers and advancing EDA flows and automation to improve design