Sr. ASIC Design Engineer

Anysilicon; Roseville, Northern (CA, KY); Hybrid; USD 140,000 - 200,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a Senior ASIC Design Engineer to join its Networking Silicon group in Roseville, CA. This onsite role focuses on developing advanced networking chips for routers and switches in a fast-paced environment.

You will drive micro-architecture, collaborate across verification and physical design teams, and mentor junior engineers while delivering high-performance silicon.

Qualifications

• Bachelor’s degree in Electrical Engineering with 5+ years of relevant ASIC design experience.
• Strong analytical and problem-solving skills.
• Knowledge of computer architecture and networking protocols is a plus.
• Proficient coding skills in Verilog/SystemVerilog.
• Familiarity with synthesis, lint, and other EDA tools is desired.

Responsibilities

• Develop detailed micro-architecture specifications from functional specs meeting power/area targets.
• Write functional coverage and SystemVerilog Assertions (SVA) for verification.
• Collaborate with Physical Design for floorplanning and timing closure.
• Work with Verification to ensure full validation of design blocks.
• Mentor and provide guidance to new engineers and interns.

Skills

Verilog/SystemVerilog

Python/Perl

AI tooling experience

Education

Bachelor’s in Electrical Engineering

Master’s preferred

Tools

EDA tools

Synthesis

Job description

Job Description:

Hewlett Packard Enterprise (HPE) is seeking a Senior ASIC Design Engineer to join its Networking Silicon group, focusing on the development of advanced networking chips for routers and switches. This role is primarily onsite at an HPE office, emphasizing collaboration and innovation in a fast-paced environment. HPE values diverse backgrounds and offers a culture that supports personal and professional growth.

Responsibilities:

• Develop detailed micro-architecture specifications from functional specifications that meet power and area requirements.
• Write functional coverage and SystemVerilog Assertions (SVA) to assist in verification and catch corner case bugs.
• Collaborate with the Physical Design team for optimal floorplan and timing closure, identifying and fixing timing issues in RTL to meet frequency targets.
• Work with the Verification team to ensure full validation of design blocks.
• Mentor and provide guidance to new engineers and interns.

Qualifications:

• Bachelor’s degree in Electrical Engineering (Master’s preferred) with 5+ years of relevant experience.
• Strong analytical and problem-solving skills.
• Knowledge of computer architecture and networking protocols is a plus.
• Proficient coding skills in Verilog/System Verilog from coursework or prior experience.
• Familiarity with synthesis, lint, and other EDA tools is desired.
• Excellent written and verbal communication skills.

Skills:

• Proficiency in Verilog/System Verilog.
• Knowledge of Perl/Python is a plus.
• Experience with AI agentic tools is a plus.