Senior ASIC Design Engineer: End-to-End PPA/PD

QUALCOMM, Inc.; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Annual discretionary bonus

Annual RSU grants

Competitive benefits

Job summary

Qualcomm Technologies, Inc. seeks a seasoned engineer with 5–10 years of hands-on experience in Synthesis, Place and Route (PnR) and Physical Design to optimize PPA across the design flow.

You will work across synthesis and PD boundary to enhance timing, power, and area in multi-clock domain designs. Ideal candidates have node-traction expertise, strong scripting skills, and familiarity with Innovus/ICC2 and Fusion Genus flows, delivering robust QoR and close collaboration with leadership across

Qualifications

• Bachelor’s degree in Science, Engineering, or related field with 4+ years of ASIC design experience.
• Master’s/PhD with 3+ years is also acceptable.
• Experience with timing closure, synthesis, and PD flows required.

Responsibilities

• Drive end-to-end PPA optimization across synthesis and physical design.
• Manage multi-patterning, CTS, routing, and timing constraints across MCMM designs.
• Collaborate across PD and EDA tools to balance area, power, and performance.

Skills

Python/Tcl

AI usage

Version control

Education

Bachelor’s degree in Science/Engineering

Master’s degree in Science/Engineering

PhD in Science/Engineering

Tools

Innovus

ICC2

Fusion Compiler

Genus

Primetime/ Tempus

Job description

Qualcomm Technologies, Inc. seeks a seasoned engineer with 5–10 years of hands-on experience in Synthesis, Place and Route (PnR) and Physical Design to optimize PPA across the design flow.

You will work across synthesis and PD boundary to enhance timing, power, and area in multi-clock domain designs. Ideal candidates have node-traction expertise, strong scripting skills, and familiarity with Innovus/ICC2 and Fusion Genus flows, delivering robust QoR and close collaboration with leadership across