Staff CPU Physical Design CAD Engineer - PPA Leader

Qualcomm; Santa Clara (CA); On-site; USD 209,000 - 314,000; Full time

Job summary

Qualcomm Technologies, Inc. in Santa Clara, CA is hiring a CPU Physical Design CAD engineer to build and support world-class place-and-route flows. You will ensure industry-leading power, performance and area for our custom CPUs.

The role requires hands-on experience with high-performance PD flows, Tcl/Python scripting, and collaboration with global teams to optimize PPA. Knowledge of Cadence Innovus and advanced tech nodes is essential.

Qualifications

• Masters/PhD in a related field with 5+ years of hardware/engineering experience.
• Experience with place-and-route of high-performance chips in either design or CAD roles.
• Strong scripting via Tcl/Python and automation experience.

Responsibilities

• Develop, integrate and release new features in high-performance place-and-route CAD flow.
• Architect and recommend methodology improvements to optimize power, performance and area.
• Maintain, support and debug implementation flows and resolve project issues.
• Collaborate with global CPU physical design teams and provide tool/flow support.
• Engage with EDA vendors to define roadmap and resolve tool issues.

Skills

place-and-route

automation

timing analysis

digital design

physical verification

PPA

Python

Tcl

regressing flows

Education

Master's degree in Electrical Engineering, Computer Engineering, Computer Science

PhD in Electrical Engineering, Computer Engineering, Computer Science

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science

Tools

Cadence Innovus

Job description

Qualcomm Technologies, Inc. in Santa Clara, CA is hiring a CPU Physical Design CAD engineer to build and support world-class place-and-route flows. You will ensure industry-leading power, performance and area for our custom CPUs.

The role requires hands-on experience with high-performance PD flows, Tcl/Python scripting, and collaboration with global teams to optimize PPA. Knowledge of Cadence Innovus and advanced tech nodes is essential.