Senior ASIC PnR & Physical Design Engineer (PPA & Power)

Qualcomm; Austin, Northern (TX, KY); Hybrid; USD 140,000 - 210,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an experienced engineer to drive PPA optimization across synthesis to physical design. You will work on advanced nodes, handle timing closures, and balance area, power, and performance across multi-clock designs.

The role requires deep expertise in PnR and synthesis tools, with leadership interactions and a focus on end-to-end optimization. Join a team delivering cutting-edge core technologies.

Qualifications

• Bachelor's degree in Science, Engineering, or related field plus 4+ years in ASIC design/verification.
• Master's degree in Science, Engineering, or related field plus 3+ years in ASIC design/verification.
• PhD in Science, Engineering, or related field plus 2+ years in ASIC design/verification.
• Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
• 6+ years of ASIC design/verification experience.
• 2+ years with architecture and design tools.
• 2+ years scripting/programming languages.
• 2+ years with design verification methods.
• 1+ year engaging with senior leadership.

Responsibilities

• Drive PPA optimization across synthesis to PD and close boundary handoffs.
• Tackle node-specific PPA challenges and timing closure.
• Write and tune timing constraints for synthesis, STA, and pipelining.
• Lead MCMM timing closure across multiple clocks and domains.
• Focus on aggressive area recovery and leakage/power reduction.
• Collaborate across teams to balance QoR and physical implementation.

Skills

Python/Tcl

AI usage

Innovus

ICC2

Fusion Compiler

Genus

CTS

Timing constraints

Synthesis

QoR optimization

Floorplanning

Placement

CTS routing

Equivalence Checking

Power/Performance/Area

Computer architecture

High-speed design

Education

Bachelor's degree

Master's degree

PhD

Tools

Fusion Compiler

Genus

Innovus

ICC2

PrimeTime

Tempus

Job description

Qualcomm Technologies, Inc. is seeking an experienced engineer to drive PPA optimization across synthesis to physical design. You will work on advanced nodes, handle timing closures, and balance area, power, and performance across multi-clock designs.

The role requires deep expertise in PnR and synthesis tools, with leadership interactions and a focus on end-to-end optimization. Join a team delivering cutting-edge core technologies.