Senior ASIC Design Engineer - Digital & Mixed-Signal Lead

MARICI Solutions GmbH; Dallas (TX); Hybrid; USD 140,000 - 210,000; Full time

Job summary

MARICI Solutions GmbH in Plano, Texas, is seeking a Senior ASIC Design Engineer/Senior Staff Digital Design Engineer to lead architecture, RTL implementation, and silicon bring-up for complex digital subsystems. The role requires RTL expertise, Verilog/SystemVerilog proficiency, and UVM verification experience.

Collaborate across system, analog, and physical design teams to meet stringent PPA targets and deliver first-pass silicon quality. Hybrid work arrangement offered.

Qualifications

• BS or MS in Electronics, Electrical Engineering, or VLSI.
• 5+ years of Digital IC Design experience with RTL, verification, and silicon debug.
• Strong Verilog/SystemVerilog expertise and design methodologies.
• Experience with UVM-based verification and various verification flows.
• Proficiency in low-power and PPA optimization techniques.
• Hands-on with industry-standard interfaces and tools.

Responsibilities

• Lead architecture and RTL implementation for complex digital subsystems.
• Translate requirements into optimized Verilog/SystemVerilog designs while hitting PPA targets.
• Drive verification and signoff using Lint, CDC/RDC, Formal, and LEC flows.
• Collaborate across system, analog, and physical design teams to meet specs.
• Lead silicon bring-up, debugging, and design-to-silicon correlation.
• Present architecture and drive technical reviews with customers.

Skills

RTL design

Verilog/SystemVerilog

Digital IC Design

UVM verification

Synthesis

Timing analysis

Low-power design

PPA optimization

Python scripting

Shell scripting

Education

B.Tech/M.Tech in Electronics/EE/VLSI

Tools

Xcelium

Genus

SpyGlass

OneSpin/JasperGold

Innovus

PrimeTime/Tempus

Cadence Virtuoso

Job description

MARICI Solutions GmbH in Plano, Texas, is seeking a Senior ASIC Design Engineer/Senior Staff Digital Design Engineer to lead architecture, RTL implementation, and silicon bring-up for complex digital subsystems. The role requires RTL expertise, Verilog/SystemVerilog proficiency, and UVM verification experience.

Collaborate across system, analog, and physical design teams to meet stringent PPA targets and deliver first-pass silicon quality. Hybrid work arrangement offered.