Lead ASIC Digital Architect - DDR/PCIe/UCIe

Synopsys, Inc.; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Job summary

Synopsys, Inc. is seeking an experienced ASIC Digital Architect to drive the future of semiconductor technology in Austin. You will define and lead RTL design and verification at chip and block levels, shaping architectures for DDR, PCIe, CXL, UAL, and UCIe IO protocols while mentoring junior engineers.

You will collaborate with cross-functional teams to ensure successful integration, apply advanced design methodologies, and influence strategic decisions across Synopsys' digital design efforts.

Qualifications

• Extensive experience in ASIC RTL design.
• Deep knowledge of DDR, PCIe, UAL, UCIe IO protocols.
• Ability to define and execute architecture for protocols like UAL.
• Strong communication and mentoring skills.

Responsibilities

• Define and develop ASIC RTL design and verification at chip and block levels.
• Create and execute design plans for complex digital designs focusing on DDR, PCIe, CXL, UAL, UCIe IO protocols.
• Collaborate with cross-functional teams for seamless integration.
• Utilize advanced design and verification methodologies to achieve high quality results.
• Mentor junior engineers and promote best practices.

Skills

ASIC RTL design

DDR IO protocols

PCIe/UCIe/UAL

Mentoring

Independent work

Education

BSEE or BSCE +12 years

Advanced degree +10 years

Tools

Advanced digital design tools

Job description

Synopsys, Inc. is seeking an experienced ASIC Digital Architect to drive the future of semiconductor technology in Austin. You will define and lead RTL design and verification at chip and block levels, shaping architectures for DDR, PCIe, CXL, UAL, and UCIe IO protocols while mentoring junior engineers.

You will collaborate with cross-functional teams to ensure successful integration, apply advanced design methodologies, and influence strategic decisions across Synopsys' digital design efforts.