Senior ASIC Design Engineer

MARICI Solutions GmbH; Dallas (TX); Hybrid; USD 140,000 - 210,000; Full time

Job summary

MARICI Solutions GmbH in Plano, Texas, is seeking a Senior ASIC Design Engineer/Senior Staff Digital Design Engineer to lead architecture, RTL implementation, and silicon bring-up for complex digital subsystems. The role requires RTL expertise, Verilog/SystemVerilog proficiency, and UVM verification experience.

Collaborate across system, analog, and physical design teams to meet stringent PPA targets and deliver first-pass silicon quality. Hybrid work arrangement offered.

Qualifications

• BS or MS in Electronics, Electrical Engineering, or VLSI.
• 5+ years of Digital IC Design experience with RTL, verification, and silicon debug.
• Strong Verilog/SystemVerilog expertise and design methodologies.
• Experience with UVM-based verification and various verification flows.
• Proficiency in low-power and PPA optimization techniques.
• Hands-on with industry-standard interfaces and tools.

Responsibilities

• Lead architecture and RTL implementation for complex digital subsystems.
• Translate requirements into optimized Verilog/SystemVerilog designs while hitting PPA targets.
• Drive verification and signoff using Lint, CDC/RDC, Formal, and LEC flows.
• Collaborate across system, analog, and physical design teams to meet specs.
• Lead silicon bring-up, debugging, and design-to-silicon correlation.
• Present architecture and drive technical reviews with customers.

Skills

RTL design

Verilog/SystemVerilog

Digital IC Design

UVM verification

Synthesis

Timing analysis

Low-power design

PPA optimization

Python scripting

Shell scripting

Education

B.Tech/M.Tech in Electronics/EE/VLSI

Tools

Xcelium

Genus

SpyGlass

OneSpin/JasperGold

Innovus

PrimeTime/Tempus

Cadence Virtuoso

Job description

Position: Senior ASIC Design Engineer/Senior Staff Digital Design EngineerLocation: Plano, Texas - HybridEmployment type: Full-time Permanent

Job Description

• Lead the architecture, design, integration, and silicon realization of complex digital and mixed-signal subsystems from specification through production.
• Translate customer and system requirements into optimized RTL architectures and high-quality Verilog/SystemVerilog implementations while meeting PPA targets.
• Drive design quality and signoff through Lint, CDC/RDC, Formal Verification, LEC, synthesis, and timing validation.
• Collaborate with system, analog, verification, and physical design teams to define specifications and ensure successful product execution.
• Develop digital control and interface logic for ADCs, analog front-end systems, power management, sensors, and other mixed-signal IPs.
• Lead silicon bring-up, debugging, root-cause analysis, and design-to-silicon correlation to achieve first-pass silicon success.
• Serve as a key customer-facing technical lead by presenting architecture, conducting design reviews, communicating quality metrics, and driving resolution of technical issues.
• Prepare technical proposals, effort estimates, PPA projections, specifications, and design documentation.
• Provide technical leadership and drive continuous improvement in design methodologies and best practices.

Required Education and Experience

• B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI, or a related discipline.
• 5+ years of experience in Digital IC Design with strong expertise in RTL design, verification, synthesis, and silicon debug.
• Strong proficiency in Verilog/SystemVerilog and digital design methodologies.
• Proven experience designing complex state machines, control logic, data-processing modules, and mixed-signal interfaces.
• Hands-on experience with UVM-based verification.
• Strong experience with industry-standard serial interfaces, including I C, I3C, SPI, and UART.
• Expertise in low-power design techniques, PPA optimization, CDC/RDC analysis, Lint, Formal Verification, and LEC flows.
• Strong understanding of STA, synthesis, and implementation-aware design methodologies.
• Proficiency in Python, Tcl, Perl, or Shell scripting.
• Experience with Xcelium, Genus, SpyGlass, and OneSpin/JasperGold.
• Familiarity with Innovus, PrimeTime/Tempus, and DFT flows.
• Experience with ARM-based SoCs and AMBA protocols, including AXI/AHB/APB, is a strong advantage.
• Familiarity with Cadence Virtuoso and mixed-signal design environments is a plus.

Required Personal Skills

• Strong technical leadership, analytical, and problem-solving abilities.
• Excellent communication, presentation, and customer-engagement skills.
• Self-motivated, agile, results-oriented, and capable of driving projects independently.
• Effective mentor and collaborative team player.
• Ability to influence cross-functional teams and deliver in fast-paced environments.
• Passion for sensor, imaging, and mixed-signal semiconductor technologies.
• Fluent in written and spoken English.