Senior ASIC Design Engineer – DFT/DFX Architect

NVIDIA Corporation; Santa Clara (CA); On-site; USD 190,000 - 310,000; Full time

Job summary

NVIDIA Corporation in Santa Clara, CA is seeking a Senior ASIC Design Engineer - DFX to shape architecture, design, and verification of DFT IP for next‑gen SoCs. You will own fuse controller design, develop scalable DFT methodologies, and collaborate with architecture, design, verification, and backend teams.

The role requires 8+ years in SoC RTL/verification, Verilog, and DFT expertise, plus Python/Perl/Tcl proficiency and post-silicon bring-up experience.

Qualifications

• 8+ years of hands-on experience in SoC architecture, RTL design, and verification.
• Strong proficiency in micro-architecture and RTL development using Verilog (UVM experience is a plus).
• Deep expertise in DFT design, methodology, and implementation.
• Familiarity with clocking, STA, place & route, and power optimization.
• Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis.
• Proficiency in scripting languages such as Python, Perl, or Tcl.
• Excellent communication skills and a collaborative mindset—with a curiosity and passion for solving complex technical challenges.

Responsibilities

• Own the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs.
• Develop, deploy, and enhance DFT methodologies for scalability and future product needs.
• Define and align feature sets by working closely with architects, platform, and software teams.
• Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration.
• Create and execute test plans to support both functional and DFT full-chip verification.
• Support post-silicon bring-up and validation efforts including debug and issue resolution.
• Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance.

Skills

RTL design

Verification

Verilog

DFT

SoC architecture

Scripting: Python/Perl/Tcl

Post-silicon bring-up

UVM

Education

Bachelors degree in Electrical Engineering or related field

Master's degree in Electrical Engineering or related field

Tools

UVM

Job description

NVIDIA Corporation in Santa Clara, CA is seeking a Senior ASIC Design Engineer - DFX to shape architecture, design, and verification of DFT IP for next‑gen SoCs. You will own fuse controller design, develop scalable DFT methodologies, and collaborate with architecture, design, verification, and backend teams.

The role requires 8+ years in SoC RTL/verification, Verilog, and DFT expertise, plus Python/Perl/Tcl proficiency and post-silicon bring-up experience.